Renesas Electronics 9DBV0431AKILF Buffer 32-Pin QFN
- RS-stocknr.:
- 249-4404
- Fabrikantnummer:
- 9DBV0431AKILF
- Fabrikant:
- Renesas Electronics
Informatie over voorraden is momenteel niet toegankelijk
- RS-stocknr.:
- 249-4404
- Fabrikantnummer:
- 9DBV0431AKILF
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Buffer | |
| Maximum Input Frequency | 137.5MHz | |
| Mount Type | Surface | |
| Package Type | QFN | |
| Pin Count | 32 | |
| Minimum Supply Voltage | 1.7V | |
| Maximum Supply Voltage | 1.9V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Length | 5mm | |
| Standards/Approvals | RoHS | |
| Height | 1mm | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Buffer | ||
Maximum Input Frequency 137.5MHz | ||
Mount Type Surface | ||
Package Type QFN | ||
Pin Count 32 | ||
Minimum Supply Voltage 1.7V | ||
Maximum Supply Voltage 1.9V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Length 5mm | ||
Standards/Approvals RoHS | ||
Height 1mm | ||
Automotive Standard No | ||
The Renesas Electronics 9DBV0431 is a 4-output very low power buffer for 100 MHz PCIe Gen1, Gen2 and Gen3 applications. It can also be used for 50M or 125M Ethernet Applications via software frequency selection. The device has 4 output enables for clock management.
1.8 V operation: minimal power consumption
OE# pins: support DIF power management
HCSL compatible differential input: can be driven by common clock sources
LP-HCSL differential clock outputs: reduced power and board space
Programmable slew rate for each output: allows tuning for various line lengths
Programmable output amplitude: allows tuning for various application environments
Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
Outputs blocked until PLL is locked: clean system start-up
Software selectable 50 MHz or 125 MHz PLL operation: useful for Ethernet applications
Configuration can be accomplished with strapping pins: SMBus interface not required for device control
3.3 V tolerant SMBus interface works with legacy controllers
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