Nexperia 74HCT373D,653, Octal Octal D Type Latch, 8-Bit Non-Inverting, 20-Pin SO-20
- RS-stocknr.:
- 170-5429P
- Fabrikantnummer:
- 74HCT373D,653
- Fabrikant:
- Nexperia
Bulkkorting beschikbaar
Subtotaal 125 eenheden (geleverd op een doorlopende strip)*
€ 41,875
(excl. BTW)
€ 50,625
(incl. BTW)
GRATIS bezorging voor bestellingen van meer dan € 75,00
Tijdelijk niet op voorraad
- Verzending 2.000 stuk(s) vanaf 06 mei 2026
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Aantal stuks | Per stuk |
|---|---|
| 125 - 475 | € 0,335 |
| 500 - 1225 | € 0,319 |
| 1250 + | € 0,254 |
*prijsindicatie
- RS-stocknr.:
- 170-5429P
- Fabrikantnummer:
- 74HCT373D,653
- Fabrikant:
- Nexperia
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Nexperia | |
| Logic Family | 74HCT | |
| Logic Function | D Type | |
| Number of Elements per Chip | 8 | |
| Number of Channels per Chip | 8 | |
| Polarity | Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | SO-20 | |
| Pin Count | 20 | |
| Length | 13mm | |
| Maximum Operating Temperature | +125 °C | |
| Minimum Operating Supply Voltage | 4.5 V | |
| Dimensions | 13 x 7.6 x 2.45mm | |
| Minimum Operating Temperature | -40 °C | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Height | 2.45mm | |
| Width | 7.6mm | |
| Alles selecteren | ||
|---|---|---|
Merk Nexperia | ||
Logic Family 74HCT | ||
Logic Function D Type | ||
Number of Elements per Chip 8 | ||
Number of Channels per Chip 8 | ||
Polarity Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type SO-20 | ||
Pin Count 20 | ||
Length 13mm | ||
Maximum Operating Temperature +125 °C | ||
Minimum Operating Supply Voltage 4.5 V | ||
Dimensions 13 x 7.6 x 2.45mm | ||
Minimum Operating Temperature -40 °C | ||
Maximum Operating Supply Voltage 5.5 V | ||
Height 2.45mm | ||
Width 7.6mm | ||
- Land van herkomst:
- CN
The 74HC373, 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
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