Renesas Electronics 2305-1HDCG Clock Buffer 8-Pin SOIC
- RS-stocknr.:
- 263-7867
- Fabrikantnummer:
- 2305-1HDCG
- Fabrikant:
- Renesas Electronics
Bulkkorting beschikbaar
Subtotaal (1 verpakking van 10 eenheden)*
€ 5,21
(excl. BTW)
€ 6,30
(incl. BTW)
Voeg 170 eenheden toe voor gratis bezorging
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Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 10 - 10 | € 0,521 | € 5,21 |
| 20 - 40 | € 0,512 | € 5,12 |
| 50 - 90 | € 0,493 | € 4,93 |
| 100 - 280 | € 0,447 | € 4,47 |
| 290 + | € 0,437 | € 4,37 |
*prijsindicatie
- RS-stocknr.:
- 263-7867
- Fabrikantnummer:
- 2305-1HDCG
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Maximum Propagation Delay Time | 350ps | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 5 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Length | 5mm | |
| Width | 4 mm | |
| Series | IDT2305 | |
| Standards/Approvals | RoHS | |
| Height | 1.75mm | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Maximum Propagation Delay Time 350ps | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 5 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Length 5mm | ||
Width 4 mm | ||
Series IDT2305 | ||
Standards/Approvals RoHS | ||
Height 1.75mm | ||
Automotive Standard No | ||
The Renesas Electronics high-speed phase-lock loop clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. It is an 8-pin version of the accepts one reference input, and drives out five low skew clocks.
Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
No external RC network required
Power down mode
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