Renesas Electronics 9DB233AGILF Clock Buffer 20-Pin TSSOP
- RS-stocknr.:
- 263-7982
- Fabrikantnummer:
- 9DB233AGILF
- Fabrikant:
- Renesas Electronics
Bulkkorting beschikbaar
Subtotaal (1 tube van 74 eenheden)*
€ 169,904
(excl. BTW)
€ 205,572
(incl. BTW)
Voeg 74 eenheden toe voor gratis bezorging
Op voorraad
- 74 stuk(s) klaar voor verzending vanaf een andere locatie
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per tube* |
|---|---|---|
| 74 - 222 | € 2,296 | € 169,90 |
| 296 + | € 2,179 | € 161,25 |
*prijsindicatie
- RS-stocknr.:
- 263-7982
- Fabrikantnummer:
- 9DB233AGILF
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 110MHz | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Number of Outputs | 2 | |
| Minimum Supply Voltage | 3.3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | 9DB233 | |
| Length | 6.6mm | |
| Width | 4.4 mm | |
| Height | 1.2mm | |
| Standards/Approvals | RoHS | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 110MHz | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 20 | ||
Number of Outputs 2 | ||
Minimum Supply Voltage 3.3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series 9DB233 | ||
Length 6.6mm | ||
Width 4.4 mm | ||
Height 1.2mm | ||
Standards/Approvals RoHS | ||
Automotive Standard No | ||
- Land van herkomst:
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
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