Renesas Electronics 9DB106BGILFT PLL Clock Buffer 28-Pin TSSOP-28

The Renesas Electronics differential buffer is a zero delay buffer which supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT CK410 or CK505 compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options while 2 clock request pins make the device suitable for express card applications.

SMBus interface or unused outputs can be disabled here