Renesas Electronics 85102AGILF Clock Buffer, 16-Pin 7 TSSOP
- RS-stocknr.:
- 216-6207
- Fabrikantnummer:
- 85102AGILF
- Fabrikant:
- Renesas Electronics
Momenteel niet beschikbaar
We weten niet of dit item nog op voorraad komt, RS is van plan dit binnenkort uit ons assortiment te halen.
- RS-stocknr.:
- 216-6207
- Fabrikantnummer:
- 85102AGILF
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | No | |
| Height | 1mm | |
| Width | 4.4 mm | |
| Length | 5mm | |
| Series | 85102A | |
| Maximum Output Frequency | 200MHz | |
| Number of Outputs | 7 | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals No | ||
Height 1mm | ||
Width 4.4 mm | ||
Length 5mm | ||
Series 85102A | ||
Maximum Output Frequency 200MHz | ||
Number of Outputs 7 | ||
Automotive Standard No | ||
The Renesas Electronics 85102I is a low skew, high performance 1-to-2 Differential-to-HCSL fanout buffer. The 85102I has a differential clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85102I ideal for those applications demanding well defi ned performance and repeatability.
Two 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 65ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)