Renesas Electronics 854S006AGILF Clock Buffer, 24-Pin 6 SOIC
- RS-stocknr.:
- 216-6214
- Fabrikantnummer:
- 854S006AGILF
- Fabrikant:
- Renesas Electronics
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€ 21,83
(excl. BTW)
€ 26,41
(incl. BTW)
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|---|---|
| 1 - 9 | € 21,83 |
| 10 - 24 | € 20,05 |
| 25 - 49 | € 19,20 |
| 50 - 99 | € 18,49 |
| 100 + | € 16,95 |
*prijsindicatie
- RS-stocknr.:
- 216-6214
- Fabrikantnummer:
- 854S006AGILF
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Minimum Supply Voltage | 3V | |
| Pin Count | 24 | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | 854S006A | |
| Height | 1mm | |
| Length | 7.8mm | |
| Standards/Approvals | No | |
| Width | 4.4 mm | |
| Number of Outputs | 6 | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type SOIC | ||
Minimum Supply Voltage 3V | ||
Pin Count 24 | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series 854S006A | ||
Height 1mm | ||
Length 7.8mm | ||
Standards/Approvals No | ||
Width 4.4 mm | ||
Number of Outputs 6 | ||
Automotive Standard No | ||
The Renesas Electronics 854S006 is a low skew, high performance 1-to-6, Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept most standard differential input levels. The 854S006 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 854S006 ideal for those clock distribution applications demanding well defined performance and repeatability.
Six differential LVDS outputs
One differential clock input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
Output Skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature
