Renesas Electronics 9FGV0441AKILF PLL Clock Generator 4 32-Pin VFQFPN
- RS-stocknr.:
- 262-9023
- Fabrikantnummer:
- 9FGV0441AKILF
- Fabrikant:
- Renesas Electronics
Afbeelding representeert productcategorie
Bulkkorting beschikbaar
Subtotaal (1 tray van 490 eenheden)*
€ 847,70
(excl. BTW)
€ 1.024,10
(incl. BTW)
GRATIS bezorging voor bestellingen van meer dan € 90,00
Op voorraad
- Plus verzending 980 stuk(s) vanaf 04 mei 2026
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per tray* |
|---|---|---|
| 490 - 490 | € 1,73 | € 847,70 |
| 980 + | € 1,522 | € 745,78 |
*prijsindicatie
- RS-stocknr.:
- 262-9023
- Fabrikantnummer:
- 9FGV0441AKILF
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | PLL Clock Generator | |
| Mount Type | Surface | |
| Package Type | VFQFPN | |
| Pin Count | 32 | |
| Maximum Input Frequency | 27MHz | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | 9FGV0441 | |
| Length | 4mm | |
| Standards/Approvals | RoHS | |
| Height | 1mm | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type PLL Clock Generator | ||
Mount Type Surface | ||
Package Type VFQFPN | ||
Pin Count 32 | ||
Maximum Input Frequency 27MHz | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series 9FGV0441 | ||
Length 4mm | ||
Standards/Approvals RoHS | ||
Height 1mm | ||
Automotive Standard No | ||
The Renesas Electronics PCIE GEN123 CLK GEN is an 4-output very low power clock generator for PCIe Gen1–4 applications with integrated output terminations providing Zo = 100Ω. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.
Integrated terminations provide 100Ω differential Zo reduced component count and board space
1.8V operation reduced power consumption
OE pins support DIF power management
LP-HCSL differential clock outputs reduced power and board space
Programmable slew rate for each output allows tuning for various line lengths
Programmable output amplitude allows tuning for various application environments
DIF outputs blocked until PLL is locked clean system start-up
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