Microchip LAN8650B1T-E/LMX, Ethernet Transceiver, 100Mbps, Serial-SPI, 1.2 V, 24-Pin VQFN
- RS-stocknr.:
- 333-087
- Fabrikantnummer:
- LAN8650B1T-E/LMX
- Fabrikant:
- Microchip
Subtotaal (1 rol van 5000 eenheden)*
€ 21.025,00
(excl. BTW)
€ 25.440,00
(incl. BTW)
GRATIS bezorging voor bestellingen van meer dan € 75,00
Tijdelijk niet op voorraad
- Verzending vanaf 16 februari 2026
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per rol* |
|---|---|---|
| 5000 + | € 4,205 | € 21.025,00 |
*prijsindicatie
- RS-stocknr.:
- 333-087
- Fabrikantnummer:
- LAN8650B1T-E/LMX
- Fabrikant:
- Microchip
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Microchip | |
| Physical Network Type | IEEE802.3 | |
| Host Interface | Serial-SPI | |
| Communication Mode | Half Duplex | |
| Data Rate | 100Mbps | |
| Package Type | VQFN | |
| Pin Count | 24 | |
| Typical Operating Supply Voltage | 1.2 V | |
| Alles selecteren | ||
|---|---|---|
Merk Microchip | ||
Physical Network Type IEEE802.3 | ||
Host Interface Serial-SPI | ||
Communication Mode Half Duplex | ||
Data Rate 100Mbps | ||
Package Type VQFN | ||
Pin Count 24 | ||
Typical Operating Supply Voltage 1.2 V | ||
- Land van herkomst:
- TH
The Microchip LAN8650 combines a Media Access Controller and an Ethernet PHY to enable low‑cost microcontrollers, including those without an onboard MAC, to access 10BASE‑T1S networks. The common standard Serial Peripheral Interface of the LAN8650 allows interfacing with nearly any microcontroller, so that the transfer of Ethernet packets and LAN8650 control/status commands are performed over a single, serial interface. SPI also requires only 4 pins, enabling a simpler hardware interface with fewer pins than MII or RMII.
Internal wall clock
Event generation and event capture synchronized to the wall clock
Phase adjuster for the wall clock to minimize microcontroller overhead
Packet timestamping
Half duplex point to point link segments up to at least 15m
Event generation and event capture synchronized to the wall clock
Phase adjuster for the wall clock to minimize microcontroller overhead
Packet timestamping
Half duplex point to point link segments up to at least 15m
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