Microchip LAN8651B1-E/LMX, Ethernet Controller 10 Mbps SPI, 32-Pin 3.3 V VQFN-32
- RS-stocknr.:
- 352-163
- Fabrikantnummer:
- LAN8651B1-E/LMX
- Fabrikant:
- Microchip
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€ 4,31
(excl. BTW)
€ 5,22
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- Plus verzending 305 stuk(s) vanaf 03 maart 2026
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Aantal stuks | Per stuk |
|---|---|
| 1 - 9 | € 4,31 |
| 10 + | € 3,88 |
*prijsindicatie
- RS-stocknr.:
- 352-163
- Fabrikantnummer:
- LAN8651B1-E/LMX
- Fabrikant:
- Microchip
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Microchip | |
| Maximum Data Rate | 10Mbps | |
| Product Type | Ethernet Controller | |
| Communication Mode | Half Duplex | |
| Interface Type | SPI | |
| Standard Supported | IEEE | |
| Package Type | VQFN-32 | |
| Pin Count | 32 | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | IEEE Std 802.1AS, IEEE Std 1588 | |
| Alles selecteren | ||
|---|---|---|
Merk Microchip | ||
Maximum Data Rate 10Mbps | ||
Product Type Ethernet Controller | ||
Communication Mode Half Duplex | ||
Interface Type SPI | ||
Standard Supported IEEE | ||
Package Type VQFN-32 | ||
Pin Count 32 | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals IEEE Std 802.1AS, IEEE Std 1588 | ||
- Land van herkomst:
- TH
The Microchip MAC-PHY Ethernet Controller with SPI combines a Media Access Controller (MAC) and an Ethernet PHY to enable low‑cost microcontrollers, including those without an onboard MAC, to access 10BASE‑T1S networks. The common standard Serial Peripheral Interface (SPI) of the LAN8650 allows interfacing with nearly any microcontroller, so that the transfer of Ethernet packets and LAN8650 control/status commands are performed over a single, serial interface. SPI also requires only 4 pins, enabling a simpler hardware interface with fewer pins than MII or RMII.
Internal wall clock
Event generation and event capture synchronized to the wall clock
Phase adjuster for the wall clock to minimize microcontroller overhead
Packet timestamping
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