Nexperia 74HC73D-Q100J Flip Flop IC HC, CMOS, 14-Pin SO-14
- RS-stocknr.:
- 243-4416
- Fabrikantnummer:
- 74HC73D-Q100J
- Fabrikant:
- Nexperia
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Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 25 - 25 | € 0,352 | € 8,80 |
| 50 - 75 | € 0,345 | € 8,63 |
| 100 - 225 | € 0,27 | € 6,75 |
| 250 - 975 | € 0,252 | € 6,30 |
| 1000 + | € 0,171 | € 4,28 |
*prijsindicatie
- RS-stocknr.:
- 243-4416
- Fabrikantnummer:
- 74HC73D-Q100J
- Fabrikant:
- Nexperia
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Nexperia | |
| Logic Family | HC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | CMOS | |
| Polarity | Negative | |
| Mount Type | Surface | |
| Package Type | SO-14 | |
| Minimum Supply Voltage | 2V | |
| Pin Count | 14 | |
| Maximum Supply Voltage | 6V | |
| Trigger Type | Negative Edge | |
| Flip-Flop Type | JK Type | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | HBM JESD22-A114F, AEC-Q100 (Grade 1), JEDEC Standards JESD8C (2.7 V to 3.6 V), JESD7A (2.0 V to 6.0 V), MM JESD22-A115-A | |
| Series | 74HC73-Q100 | |
| Automotive Standard | AEC-Q100 Grade 1 | |
| Alles selecteren | ||
|---|---|---|
Merk Nexperia | ||
Logic Family HC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type CMOS | ||
Polarity Negative | ||
Mount Type Surface | ||
Package Type SO-14 | ||
Minimum Supply Voltage 2V | ||
Pin Count 14 | ||
Maximum Supply Voltage 6V | ||
Trigger Type Negative Edge | ||
Flip-Flop Type JK Type | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals HBM JESD22-A114F, AEC-Q100 (Grade 1), JEDEC Standards JESD8C (2.7 V to 3.6 V), JESD7A (2.0 V to 6.0 V), MM JESD22-A115-A | ||
Series 74HC73-Q100 | ||
Automotive Standard AEC-Q100 Grade 1 | ||
The Nexperia dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output high. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
CMOS low-power dissipation
Wide supply voltage range from 2.0 to 6.0 V
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
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