Renesas Electronics 74FCT573CTSOG 8-Bit Octal D Type Latch, Transparent, CMOS, 20-Pin SOIC
- RS-stocknr.:
- 263-7966
- Fabrikantnummer:
- 74FCT573CTSOG
- Fabrikant:
- Renesas Electronics
Bulkkorting beschikbaar
Subtotaal (1 verpakking van 5 eenheden)*
€ 4,19
(excl. BTW)
€ 5,07
(incl. BTW)
Informatie over voorraden is momenteel niet toegankelijk - Controleer het later nog eens opnieuw
Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 5 - 5 | € 0,838 | € 4,19 |
| 10 - 20 | € 0,754 | € 3,77 |
| 25 - 105 | € 0,718 | € 3,59 |
| 110 + | € 0,702 | € 3,51 |
*prijsindicatie
- RS-stocknr.:
- 263-7966
- Fabrikantnummer:
- 74FCT573CTSOG
- Fabrikant:
- Renesas Electronics
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Renesas Electronics | |
| Product Type | Octal D Type Latch | |
| Logic Family | 74FCT | |
| Logic Function | D Type | |
| Latch Mode | Transparent | |
| Number of Bits | 8 | |
| Number of Channels | 20 | |
| Output Type | CMOS | |
| Package Type | SOIC | |
| Pin Count | 20 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Propagation Delay Time @ CL | 4.2ns | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | No | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Renesas Electronics | ||
Product Type Octal D Type Latch | ||
Logic Family 74FCT | ||
Logic Function D Type | ||
Latch Mode Transparent | ||
Number of Bits 8 | ||
Number of Channels 20 | ||
Output Type CMOS | ||
Package Type SOIC | ||
Pin Count 20 | ||
Minimum Operating Temperature -40°C | ||
Maximum Propagation Delay Time @ CL 4.2ns | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals No | ||
Automotive Standard No | ||
- Land van herkomst:
- TW
The Renesas Electronics octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when latch enable is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the output enable is low. When OE is high, the bus output is in the high-impedance state.
Low input and output leakage ≤1μA
CMOS power levels
High drive outputs
Power off disable outputs permit live insertion
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