Nexperia HEF4071BT,653, 4 2-Input OR Gate Logic Gate, 14-Pin SO-14
- RS-stocknr.:
- 625-398
- Fabrikantnummer:
- HEF4071BT,653
- Fabrikant:
- Nexperia
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(incl. BTW)
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Aantal stuks | Per stuk |
|---|---|
| 1 - 24 | € 0,28 |
| 25 - 99 | € 0,25 |
| 100 + | € 0,23 |
*prijsindicatie
- RS-stocknr.:
- 625-398
- Fabrikantnummer:
- HEF4071BT,653
- Fabrikant:
- Nexperia
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Nexperia | |
| Product Type | Logic Gate | |
| Logic Function | OR Gate | |
| Mount Type | Surface | |
| Number of Elements | 4 | |
| Number of Inputs per Gate | 2 | |
| Schmitt Trigger Input | No | |
| Package Type | SO-14 | |
| Pin Count | 14 | |
| Logic Family | CMOS | |
| Minimum Operating Temperature | -40°C | |
| Maximum High Level Output Current | -4.2mA | |
| Maximum Propagation Delay Time @ CL | 120ns | |
| Maximum Operating Temperature | 125°C | |
| Maximum Supply Voltage | 18V | |
| Series | HEF4071B | |
| Standards/Approvals | JEDEC JESD 13-B | |
| Length | 8.75mm | |
| Minimum Supply Voltage | 3V | |
| Maximum Low Level Output Current | 4.2mA | |
| Output Type | Standard | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Nexperia | ||
Product Type Logic Gate | ||
Logic Function OR Gate | ||
Mount Type Surface | ||
Number of Elements 4 | ||
Number of Inputs per Gate 2 | ||
Schmitt Trigger Input No | ||
Package Type SO-14 | ||
Pin Count 14 | ||
Logic Family CMOS | ||
Minimum Operating Temperature -40°C | ||
Maximum High Level Output Current -4.2mA | ||
Maximum Propagation Delay Time @ CL 120ns | ||
Maximum Operating Temperature 125°C | ||
Maximum Supply Voltage 18V | ||
Series HEF4071B | ||
Standards/Approvals JEDEC JESD 13-B | ||
Length 8.75mm | ||
Minimum Supply Voltage 3V | ||
Maximum Low Level Output Current 4.2mA | ||
Output Type Standard | ||
Automotive Standard No | ||
- Land van herkomst:
- CN
The Nexperia Quad 2-input OR gate is designed with input clamp diodes, allowing the use of current limiting resistors to safely interface with input voltages higher than VDD. It provides standard OR logic functionality across four independent gates.
Fully static operation
CMOS low power dissipation
High noise immunity
Standardized symmetrical output characteristics
Inputs and outputs are protected against electrostatic effects
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