Toshiba, Decoder, 16-Pin TSSOP
- RS-stocknr.:
- 171-3318
- Fabrikantnummer:
- 74VHC138FT
- Fabrikant:
- Toshiba
Subtotaal (1 rol van 2500 eenheden)*
€ 282,50
(excl. BTW)
€ 342,50
(incl. BTW)
GRATIS bezorging voor bestellingen van meer dan € 75,00
Op voorraad
- 2.500 stuk(s) klaar voor verzending vanaf een andere locatie
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Aantal stuks | Per stuk | Per rol* |
|---|---|---|
| 2500 + | € 0,113 | € 282,50 |
*prijsindicatie
- RS-stocknr.:
- 171-3318
- Fabrikantnummer:
- 74VHC138FT
- Fabrikant:
- Toshiba
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Toshiba | |
| Logic Family | 74VHC | |
| Product Type | Decoder | |
| Number of Inputs | 3 | |
| Logic Function | Decoder | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Number of Outputs | 34 | |
| Minimum Supply Voltage | 2V | |
| Maximum Supply Voltage | 5.5V | |
| Minimum Operating Temperature | 125°C | |
| Maximum Operating Temperature | -40°C | |
| Width | 4.4 mm | |
| Length | 5mm | |
| Height | 1.2mm | |
| Series | 74VHC | |
| Standards/Approvals | No | |
| Automotive Standard | AEC-Q100 | |
| Alles selecteren | ||
|---|---|---|
Merk Toshiba | ||
Logic Family 74VHC | ||
Product Type Decoder | ||
Number of Inputs 3 | ||
Logic Function Decoder | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Number of Outputs 34 | ||
Minimum Supply Voltage 2V | ||
Maximum Supply Voltage 5.5V | ||
Minimum Operating Temperature 125°C | ||
Maximum Operating Temperature -40°C | ||
Width 4.4 mm | ||
Length 5mm | ||
Height 1.2mm | ||
Series 74VHC | ||
Standards/Approvals No | ||
Automotive Standard AEC-Q100 | ||
The 74VHC138FT is an advanced high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Wide operating temperature: Topr = -40 to 125
High speed: Propagation delay time = 3.8 ns (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 2.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28 % VCC (min)
Power-down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 5.5 V
Low noise: V = 0.8 V (max)