Nexperia HEF4013BT,652 Dual D Type Flip Flop IC, 14-Pin SOIC
- RS-stocknr.:
- 103-8389
- Fabrikantnummer:
- HEF4013BT,652
- Fabrikant:
- Nexperia
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Elk (op een haspel van 2500)
€ 300,00
(excl. BTW)
€ 363,00
(incl. BTW)
- RS-stocknr.:
- 103-8389
- Fabrikantnummer:
- HEF4013BT,652
- Fabrikant:
- Nexperia
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Nexperia | |
| Logic Family | 4000 | |
| Logic Function | D Type | |
| Input Type | Single Ended | |
| Output Signal Type | Differential | |
| Triggering Type | Positive Edge | |
| Polarity | Inverting, Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | SOIC | |
| Pin Count | 14 | |
| Set/Reset | Yes | |
| Number of Elements per Chip | 2 | |
| Maximum Propagation Delay Time @ Maximum CL | 220 ns @ 5 V | |
| Dimensions | 8.75 x 4 x 1.45mm | |
| Maximum Operating Supply Voltage | 15 V | |
| Width | 4mm | |
| Minimum Operating Supply Voltage | 3 V | |
| Maximum Operating Temperature | +125 °C | |
| Length | 8.75mm | |
| Minimum Operating Temperature | -40 °C | |
| Height | 1.45mm | |
| Propagation Delay Test Condition | 50pF | |
| Alles selecteren | ||
|---|---|---|
Merk Nexperia | ||
Logic Family 4000 | ||
Logic Function D Type | ||
Input Type Single Ended | ||
Output Signal Type Differential | ||
Triggering Type Positive Edge | ||
Polarity Inverting, Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type SOIC | ||
Pin Count 14 | ||
Set/Reset Yes | ||
Number of Elements per Chip 2 | ||
Maximum Propagation Delay Time @ Maximum CL 220 ns @ 5 V | ||
Dimensions 8.75 x 4 x 1.45mm | ||
Maximum Operating Supply Voltage 15 V | ||
Width 4mm | ||
Minimum Operating Supply Voltage 3 V | ||
Maximum Operating Temperature +125 °C | ||
Length 8.75mm | ||
Minimum Operating Temperature -40 °C | ||
Height 1.45mm | ||
Propagation Delay Test Condition 50pF | ||
The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs. The outputs are buffered for best system performance. The clock input’s Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options