Nexperia 74LVC273PW,118 1 Flip Flop IC 74LVC, D Type, 20-Pin TSSOP
- RS-stocknr.:
- 170-5348
- Fabrikantnummer:
- 74LVC273PW,118
- Fabrikant:
- Nexperia
Subtotaal (1 verpakking van 25 eenheden)*
€ 6,60
(excl. BTW)
€ 7,98
(incl. BTW)
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Aantal stuks | Per stuk | Per verpakking* |
|---|---|---|
| 25 + | € 0,264 | € 6,60 |
*prijsindicatie
- RS-stocknr.:
- 170-5348
- Fabrikantnummer:
- 74LVC273PW,118
- Fabrikant:
- Nexperia
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Nexperia | |
| Product Type | Flip Flop IC | |
| Logic Family | 74LVC | |
| Input Type | Single Ended | |
| Output Type | D Type | |
| Clock Frequency | 150MHz | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Minimum Supply Voltage | 1.65V | |
| Maximum Supply Voltage | 3.6V | |
| Pin Count | 20 | |
| Maximum Propagation Delay Time @ CL | 10.5ns | |
| Minimum Operating Temperature | -40°C | |
| Trigger Type | Positive Edge | |
| Flip-Flop Type | D Flip-Flop | |
| Maximum Operating Temperature | 125°C | |
| Number of Elements per Chip | 1 | |
| Length | 6.6mm | |
| Standards/Approvals | No | |
| Height | 950μm | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Nexperia | ||
Product Type Flip Flop IC | ||
Logic Family 74LVC | ||
Input Type Single Ended | ||
Output Type D Type | ||
Clock Frequency 150MHz | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Minimum Supply Voltage 1.65V | ||
Maximum Supply Voltage 3.6V | ||
Pin Count 20 | ||
Maximum Propagation Delay Time @ CL 10.5ns | ||
Minimum Operating Temperature -40°C | ||
Trigger Type Positive Edge | ||
Flip-Flop Type D Flip-Flop | ||
Maximum Operating Temperature 125°C | ||
Number of Elements per Chip 1 | ||
Length 6.6mm | ||
Standards/Approvals No | ||
Height 950μm | ||
Automotive Standard No | ||
- Land van herkomst:
- CN
The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and Master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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