Alliance Memory AS4C256M16D3C-10BCNTR SDRAM 4 GB Surface, 96-Pin 16 bit FBGA-96 Ball
- RS-stocknr.:
- 425-294
- Fabrikantnummer:
- AS4C256M16D3C-10BCNTR
- Fabrikant:
- Alliance Memory
Subtotaal (1 rol van 2000 eenheden)*
€ 39.640,00
(excl. BTW)
€ 47.960,00
(incl. BTW)
Informatie over voorraden is momenteel niet toegankelijk - Controleer het later nog eens opnieuw
Aantal stuks | Per stuk | Per rol* |
|---|---|---|
| 2000 + | € 19,82 | € 39.640,00 |
*prijsindicatie
- RS-stocknr.:
- 425-294
- Fabrikantnummer:
- AS4C256M16D3C-10BCNTR
- Fabrikant:
- Alliance Memory
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Alliance Memory | |
| Product Type | SDRAM | |
| Memory Size | 4GB | |
| Data Bus Width | 16bit | |
| Maximum Clock Frequency | 933MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 20ns | |
| Mount Type | Surface | |
| Package Type | FBGA-96 Ball | |
| Pin Count | 96 | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 95°C | |
| Series | AS4C256M16D3C | |
| Length | 13.5mm | |
| Height | 1.2mm | |
| Standards/Approvals | RoHS, JEDEC | |
| Minimum Supply Voltage | 1.425V | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 1.5V | |
| Alles selecteren | ||
|---|---|---|
Merk Alliance Memory | ||
Product Type SDRAM | ||
Memory Size 4GB | ||
Data Bus Width 16bit | ||
Maximum Clock Frequency 933MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 20ns | ||
Mount Type Surface | ||
Package Type FBGA-96 Ball | ||
Pin Count 96 | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 95°C | ||
Series AS4C256M16D3C | ||
Length 13.5mm | ||
Height 1.2mm | ||
Standards/Approvals RoHS, JEDEC | ||
Minimum Supply Voltage 1.425V | ||
Automotive Standard No | ||
Maximum Supply Voltage 1.5V | ||
- Land van herkomst:
- TW
The Alliance Memory 4gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Write Leveling
ZQ Calibration
RoHS compliant
Auto Refresh and Self Refresh
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