ISSI IS42S32400J-6BLI SDRAM 128 MB Surface Mount, 90-Pin 32 bit BGA
- RS-stocknr.:
- 648-081
- Fabrikantnummer:
- IS42S32400J-6BLI
- Fabrikant:
- ISSI
Subtotaal (1 eenheid)*
€ 3,72
(excl. BTW)
€ 4,50
(incl. BTW)
Informatie over voorraden is momenteel niet toegankelijk - Controleer het later nog eens opnieuw
Aantal stuks | Per stuk |
|---|---|
| 1 + | € 3,72 |
*prijsindicatie
- RS-stocknr.:
- 648-081
- Fabrikantnummer:
- IS42S32400J-6BLI
- Fabrikant:
- ISSI
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | ISSI | |
| Product Type | SDRAM | |
| Memory Size | 128MB | |
| Organisation | 1M bit | |
| Data Bus Width | 32bit | |
| Address Bus Width | 12bit | |
| Maximum Clock Frequency | 166MHz | |
| Maximum Random Access Time | 6ns | |
| Mount Type | Surface Mount | |
| Package Type | BGA | |
| Pin Count | 90 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | RoHS | |
| Series | IS42S32400J | |
| Maximum Supply Voltage | 3.6V | |
| Supply Current | 120mA | |
| Minimum Supply Voltage | 3V | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk ISSI | ||
Product Type SDRAM | ||
Memory Size 128MB | ||
Organisation 1M bit | ||
Data Bus Width 32bit | ||
Address Bus Width 12bit | ||
Maximum Clock Frequency 166MHz | ||
Maximum Random Access Time 6ns | ||
Mount Type Surface Mount | ||
Package Type BGA | ||
Pin Count 90 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals RoHS | ||
Series IS42S32400J | ||
Maximum Supply Voltage 3.6V | ||
Supply Current 120mA | ||
Minimum Supply Voltage 3V | ||
Automotive Standard No | ||
The ISSI 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V VDD and 3.3V VDDQ memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 256 columns by 32 bits. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the Ability to synchronously burst data at a high data rate with automatic column-address generation, the Ability to interleave between internal banks to hide recharge time and the capAbility to randomly change column addresses on each clock cycle during burst access.
Auto Refresh (CBR)
Self Refresh
LVTTL Interface
Random column address every clock cycle
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