Micron MT41J128M16JT-125:K SDRAM 2 GB Surface Mount, 96-Pin 16 bit FBGA
- RS-stocknr.:
- 696-929
- Fabrikantnummer:
- MT41J128M16JT-125:K
- Fabrikant:
- Micron
Subtotaal (1 eenheid)*
€ 17,98
(excl. BTW)
€ 21,76
(incl. BTW)
GRATIS bezorging voor bestellingen van meer dan € 90,00
Tijdelijk niet op voorraad
- Verzending 150 stuk(s) vanaf 24 december 2026
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Aantal stuks | Per stuk |
|---|---|
| 1 + | € 17,98 |
*prijsindicatie
- RS-stocknr.:
- 696-929
- Fabrikantnummer:
- MT41J128M16JT-125:K
- Fabrikant:
- Micron
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Micron | |
| Memory Size | 2GB | |
| Product Type | SDRAM | |
| Organisation | 128M x 16 | |
| Data Bus Width | 16bit | |
| Maximum Clock Frequency | 800MHz | |
| Number of Bits per Word | 16 | |
| Mount Type | Surface Mount | |
| Package Type | FBGA | |
| Minimum Operating Temperature | 0°C | |
| Pin Count | 96 | |
| Maximum Operating Temperature | 95°C | |
| Length | 14mm | |
| Series | MT41J | |
| Width | 8mm | |
| Standards/Approvals | RoHS | |
| Height | 1.2mm | |
| Maximum Supply Voltage | 1.575V | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 1.425V | |
| Alles selecteren | ||
|---|---|---|
Merk Micron | ||
Memory Size 2GB | ||
Product Type SDRAM | ||
Organisation 128M x 16 | ||
Data Bus Width 16bit | ||
Maximum Clock Frequency 800MHz | ||
Number of Bits per Word 16 | ||
Mount Type Surface Mount | ||
Package Type FBGA | ||
Minimum Operating Temperature 0°C | ||
Pin Count 96 | ||
Maximum Operating Temperature 95°C | ||
Length 14mm | ||
Series MT41J | ||
Width 8mm | ||
Standards/Approvals RoHS | ||
Height 1.2mm | ||
Maximum Supply Voltage 1.575V | ||
Automotive Standard No | ||
Minimum Supply Voltage 1.425V | ||
- Land van herkomst:
- TW
The Micron DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an Interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins.
Self refresh temperature
Automatic self refresh
Multipurpose register
RoHS compliant
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