Nexperia 74HC273D,653 8-Bit Latch, Addressable, D Type Flip-Flop, 20-Pin SO
- RS-stocknr.:
- 170-7978
- Fabrikantnummer:
- 74HC273D,653
- Fabrikant:
- Nexperia
Subtotaal (1 rol van 2000 eenheden)*
€ 514,00
(excl. BTW)
€ 622,00
(incl. BTW)
GRATIS bezorging voor bestellingen van meer dan € 75,00
Tijdelijk niet op voorraad
- Verzending vanaf 24 september 2026
Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.
Aantal stuks | Per stuk | Per rol* |
|---|---|---|
| 2000 + | € 0,257 | € 514,00 |
*prijsindicatie
- RS-stocknr.:
- 170-7978
- Fabrikantnummer:
- 74HC273D,653
- Fabrikant:
- Nexperia
Specificaties
Datasheets
Wetgeving en compliance
Productomschrijving
Zoek vergelijkbare producten door een of meer kenmerken te selecteren.
Alles selecteren | Attribuut | Waarde |
|---|---|---|
| Merk | Nexperia | |
| Logic Family | 74HC | |
| Product Type | Latch | |
| Latch Mode | Addressable | |
| Logic Function | D Type | |
| Number of Bits | 8 | |
| Output Type | D Type Flip-Flop | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | SO | |
| Minimum Supply Voltage | 2V | |
| Maximum Supply Voltage | 6V | |
| Pin Count | 20 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Length | 13mm | |
| Standards/Approvals | No | |
| Height | 2.45mm | |
| Width | 7.6 mm | |
| Series | 74HC | |
| Automotive Standard | No | |
| Alles selecteren | ||
|---|---|---|
Merk Nexperia | ||
Logic Family 74HC | ||
Product Type Latch | ||
Latch Mode Addressable | ||
Logic Function D Type | ||
Number of Bits 8 | ||
Output Type D Type Flip-Flop | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type SO | ||
Minimum Supply Voltage 2V | ||
Maximum Supply Voltage 6V | ||
Pin Count 20 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Length 13mm | ||
Standards/Approvals No | ||
Height 2.45mm | ||
Width 7.6 mm | ||
Series 74HC | ||
Automotive Standard No | ||
The 74HC273, 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Key applications
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems