Infineon OptiMOS N-Channel MOSFET, 19 A, 55 V Enhancement, 3-Pin TO-252 IPD15N06S2L64ATMA2

RS-stocknr.:: 214-9032
Fabrikantnummer:: IPD15N06S2L64ATMA2
Fabrikant:: Infineon

Infineon OptiMOS N-Channel MOSFET, 19 A, 55 V Enhancement, 3-Pin TO-252 IPD15N06S2L64ATMA2

Bulkkorting beschikbaar

Bekijk bulkkorting

Subtotaal (2500 eenheden, op een rol van 2500)*

€ 792,50

(excl. BTW)

€ 960,00

(incl. BTW)

GRATIS bezorging voor bestellingen van meer dan € 90,00

Op voorraad

12.500 stuk(s) klaar voor verzending vanaf een andere locatie

Heeft u meer nodig? Klik op 'Controleer leverdata' voor extra voorraad en levertijden.

Aantal stuks	Per stuk	Per rol*
2500 - 2500	€ 0,317	€ 792,50
5000 +	€ 0,301	€ 752,50

*prijsindicatie

RS-stocknr.:: 214-9032
Fabrikantnummer:: IPD15N06S2L64ATMA2
Fabrikant:: Infineon

Specificaties

Datasheets

Wetgeving en compliance

Productomschrijving

Zoek vergelijkbare producten door een of meer kenmerken te selecteren.

Alles selecteren	Attribuut	Waarde
	Merk	Infineon
	Channel Type	N
	Product Type	MOSFET
	Maximum Continuous Drain Current Id	19A
	Maximum Drain Source Voltage Vds	55V
	Package Type	TO-252
	Series	OptiMOS
	Mount Type	Surface
	Pin Count	3
	Maximum Drain Source Resistance Rds	64mΩ
	Channel Mode	Enhancement
	Typical Gate Charge Qg @ Vgs	11nC
	Maximum Gate Source Voltage Vgs	20V
	Maximum Power Dissipation Pd	47W
	Forward Voltage Vf	1.3V
	Minimum Operating Temperature	-55°C
	Maximum Operating Temperature	175°C
	Width	6.22mm
	Standards/Approvals	No
	Height	2.3mm
	Length	6.5mm
	Automotive Standard	AEC-Q101

	Alles selecteren
	Merk Infineon
	Channel Type N
	Product Type MOSFET
	Maximum Continuous Drain Current Id 19A
	Maximum Drain Source Voltage Vds 55V
	Package Type TO-252
	Series OptiMOS
	Mount Type Surface
	Pin Count 3
	Maximum Drain Source Resistance Rds 64mΩ
	Channel Mode Enhancement
	Typical Gate Charge Qg @ Vgs 11nC
	Maximum Gate Source Voltage Vgs 20V
	Maximum Power Dissipation Pd 47W
	Forward Voltage Vf 1.3V
	Minimum Operating Temperature -55°C
	Maximum Operating Temperature 175°C
	Width 6.22mm
	Standards/Approvals No
	Height 2.3mm
	Length 6.5mm
	Automotive Standard AEC-Q101

Datasheet - IPD15N06S2L64ATMA2

Infineon OptiMOS Series MOSFET, 55V Drain Source Voltage, 19A Continuous Drain Current - IPD15N06S2L64ATMA2

This MOSFET is a power switching transistor designed for high-demand automotive and industrial environments, providing controlled conduction of current in N-channel enhancement mode across a wide temperature range. It is suitable for surface‑mounted PCB designs where efficient switching and durability under elevated temperatures are required.

Features and Benefits:

• 55 V maximum drain‑source voltage for demanding voltage margins
• 19 A continuous drain current for high‑current switching performance
• 64 mΩ maximum Rds(on) for reduced conduction losses
• 47 W maximum power dissipation for robust thermal handling
• 11 nC typical gate charge for fast switching transitions
• 20 V maximum gate‑source rating for flexible gate‑drive levels

Applications

• Suitable for automotive power distribution modules
• Ideal for DC-DC converter switch stages
• Used with motor‑drive circuits in vehicles
• Can be used for high‑speed load switching in control units
• Appropriate for surface‑mount power management on Compact boards

What temperature range can it operate within?

It functions across −55 °C to 175 °C, accommodating low‑temperature starts and high‑temperature engine‑bay conditions.

How does the package support PCB assembly?

The component is supplied in a TO‑252 surface‑mount package sized 6.5 x 6.22 mm which suits automated soldering processes.

What is the channel configuration and mode of operation?

It uses an N‑type channel and operates in enhancement mode requiring a positive gate‑source voltage to conduct.

What forward conduction characteristic should designers expect?

Expect a forward voltage of 1.3 V during conduction which factors into voltage‑drop and thermal calculations.

Are there limits on gate‑drive magnitude?

The gate‑source voltage must not exceed 20 V to prevent gate‑region overstress.